Module also offered within study programmes:
General information:
Name:
Design Digital Systems in Hardware Description Languages
Course of study:
2017/2018
Code:
IES-1-604-s
Faculty of:
Computer Science, Electronics and Telecommunications
Study level:
First-cycle studies
Specialty:
-
Field of study:
Electronics and Telecommunications
Semester:
6
Profile of education:
Academic (A)
Lecture language:
English
Form and type of study:
Full-time studies
Responsible teacher:
dr inż. Rajda Paweł J. (pjrajda@agh.edu.pl)
Academic teachers:
dr inż. Kasperek Jerzy (kasperek@agh.edu.pl)
dr inż. Rajda Paweł J. (pjrajda@agh.edu.pl)
Module summary

Description of learning outcomes for module
MLO code Student after module completion has the knowledge/ knows how to/is able to Connections with FLO Method of learning outcomes verification (form of completion)
Social competence
M_K001 The student understands the need and knows the possibility of continuous training and upgrading of professional skills. ES1A_W01 Execution of laboratory classes,
Project
M_K002 The student is aware of the importance of acting in a professional manner and respect the rules of professional ethics. ES1A_W01 Execution of laboratory classes,
Project
Skills
M_U001 Student is able to optimize and improve digital electronic hardware architectures to achieve better operational parameters. ES1A_W01 Execution of laboratory classes,
Project,
Examination
M_U002 The student is able to design, simulate, run and implement electronic digital circuits with programmable devices ES1A_W01 Execution of laboratory classes,
Examination,
Project
Knowledge
M_W001 The student is familiar with the architectures used to implement basic algorithms in hardware (including data transmission), mathematical functions and operators. ES1A_W01 Execution of laboratory classes,
Examination,
Project
M_W002 The student knows how the digital electronic circuits and systems are designed. He knows the ways of modeling and simulation of such systems. He is familiar with the implementation of digital systems in programmable devices. ES1A_W01 Execution of laboratory classes,
Examination,
Project
FLO matrix in relation to forms of classes
MLO code Student after module completion has the knowledge/ knows how to/is able to Form of classes
Lecture
Audit. classes
Lab. classes
Project classes
Conv. seminar
Seminar classes
Pract. classes
Zaj. terenowe
Zaj. warsztatowe
Others
E-learning
Social competence
M_K001 The student understands the need and knows the possibility of continuous training and upgrading of professional skills. + - + - - - - - - - -
M_K002 The student is aware of the importance of acting in a professional manner and respect the rules of professional ethics. + - + - - - - - - - -
Skills
M_U001 Student is able to optimize and improve digital electronic hardware architectures to achieve better operational parameters. + - + - - - - - - - -
M_U002 The student is able to design, simulate, run and implement electronic digital circuits with programmable devices + - + - - - - - - - -
Knowledge
M_W001 The student is familiar with the architectures used to implement basic algorithms in hardware (including data transmission), mathematical functions and operators. + - + - - - - - - - -
M_W002 The student knows how the digital electronic circuits and systems are designed. He knows the ways of modeling and simulation of such systems. He is familiar with the implementation of digital systems in programmable devices. + - + - - - - - - - -
Module content
Lectures:

01. Subject, introduction, motivation, a bit of history – 2h
02. VHDL language: design units, lexical units, instructions, data types – 3h
03. VHDL language: variables, signals and simulation – 2h
04. VHDL language: synthesis and implementation – 2h
05. VHDL language: verification – 2h
06. Overview of programmable digital architectures – FPGA/SPLD / CPLD – 2h
07. Advanced VHDL – 2h

Laboratory classes:

1. Introduction to laboratory environment, credits – 2h
2. AHDL environment – tutorials: “Entry HDL and Simulation”, “State Machine Entry and Debugging”, “Mixed Mode Entry and Simulation” – 6h
3. Training project in VHDL – specification, verification, synthesis and implementation – 6h
4. Training project in VHDL – prescaler, debouncer, testbench – file operations – 2h
5. Individual project in VHDL – 14h

Project classes:
-
Student workload (ECTS credits balance)
Student activity form Student workload
Summary student workload 60 h
Module ECTS credits 3 ECTS
Participation in lectures 15 h
Participation in laboratory classes 30 h
Preparation for classes 5 h
Completion of a project 10 h
Additional information
Method of calculating the final grade:

1. In order to obtain a credit student has to obtain a positive assessment of the laboratory exercises.
2. The average of the laboratory exercises credits is calculated.
3. The Final Credit is determined, based on the formula:
if the average> 4.75 then FC = 5.0 otherwise
if you mean> 4.25 then FC = 4.5 otherwise
if the average> 3.75 then FC = 4.0 otherwise
if average> 3.25 then FC = 3.5 otherwise
FC = 3.0

Prerequisites and additional requirements:

· Knowledge of the logic theory
· Knowledge of digital electronics techniques

Recommended literature and teaching resources:

1. M. Zwoliński: „Digital System Design with VHDL”, Prentice Hall
2. K. Skahill: „VHDL for Programmable Logic”, Addison-Wesley Publishing
3. J. Bhasker: „A VHDL Synthesis primer”, AT&T
4. D. Naylor, S. Jones: „VHDL: A Logic Synthesis Approach”, Springer

Scientific publications of module course instructors related to the topic of the module:

Additional scientific publications not specified

Additional information:

None