Module also offered within study programmes:
General information:
Name:
Integrated circuits and systems
Course of study:
2017/2018
Code:
IES-1-513-s
Faculty of:
Computer Science, Electronics and Telecommunications
Study level:
First-cycle studies
Specialty:
-
Field of study:
Electronics and Telecommunications
Semester:
5
Profile of education:
Academic (A)
Lecture language:
English
Form and type of study:
Full-time studies
Responsible teacher:
prof. dr hab. inż. Kos Andrzej (kos@agh.edu.pl)
Academic teachers:
dr inż. Ireneusz Brzozowski (brzoza@agh.edu.pl)
Module summary

A student is able to perform complete design and test of integrated circuit. Also is able to choose proper technology which leads to minimization of production cost and power consumption.

Description of learning outcomes for module
MLO code Student after module completion has the knowledge/ knows how to/is able to Connections with FLO Method of learning outcomes verification (form of completion)
Social competence
M_K001 1. A student understands the importance of non-technical responsibility aspects of electronic engineer work, of particular relevance with respect to humans, animals and the whole environment. ES1A_K05 Activity during classes
Skills
M_U001 1. A student is able to design a layout of simple CMOS integrated circuit, check of design rules and to change of geometrical parameters on electrical using design software of CADENCE. ES1A_U09 Project
M_U002 2. A student is able to choose proper technology to implement a given project taking into consideration physical parameters, fabrication costs, reliability, etc. ES1A_U09 Project
Knowledge
M_W001 2. A student has knowledge in scope of MOS transistor parameters dependences on its layout. He understands influence of particular geometrical parameter changes on the transistor electrical parameters. ES1A_W02 Test
M_W002 3. A student has knowledge on fabrication of integrated circuits. He knows differences in build and parameters of discrete and integrated transistors. ES1A_W05 Test
M_W003 1. A student has general knowledge of the design of newest generation integrated circuits topography using full-custom method, i.e. bottom-up. He knows different types of technologies with considering possibilities of their various applications. ES1A_W01 Test
FLO matrix in relation to forms of classes
MLO code Student after module completion has the knowledge/ knows how to/is able to Form of classes
Lecture
Audit. classes
Lab. classes
Project classes
Conv. seminar
Seminar classes
Pract. classes
Zaj. terenowe
Zaj. warsztatowe
Others
E-learning
Social competence
M_K001 1. A student understands the importance of non-technical responsibility aspects of electronic engineer work, of particular relevance with respect to humans, animals and the whole environment. + - + - - - - - - - -
Skills
M_U001 1. A student is able to design a layout of simple CMOS integrated circuit, check of design rules and to change of geometrical parameters on electrical using design software of CADENCE. + - + - - - - - - - -
M_U002 2. A student is able to choose proper technology to implement a given project taking into consideration physical parameters, fabrication costs, reliability, etc. + - - - - - - - - - -
Knowledge
M_W001 2. A student has knowledge in scope of MOS transistor parameters dependences on its layout. He understands influence of particular geometrical parameter changes on the transistor electrical parameters. + - + - - - - - - - -
M_W002 3. A student has knowledge on fabrication of integrated circuits. He knows differences in build and parameters of discrete and integrated transistors. + - - - - - - - - - -
M_W003 1. A student has general knowledge of the design of newest generation integrated circuits topography using full-custom method, i.e. bottom-up. He knows different types of technologies with considering possibilities of their various applications. + - + - - - - - - - -
Module content
Lectures:

1. Integrated circuits creation – from idea to tests
Idea. Schematic and preliminary simulations. Layout design and geometrical rules check. Extraction of fundamental elements and comparison with schematic. Extraction of fundamental and parasitic elements and simulation. Fabrication and testing of the finished structure. Summary. Exercises.

2. CMOS integrated circuits
MOS transistors. Differences between discrete transistor and integrated one. Parasitic capacitance in CMOS circuits. Digital circuits parameters:
- Transient characteristic
- Fan-in and fan-out of a gate
- Dynamic properties
- Energy consumption
- Delay-Power product
Basic CMOS elements:
- Inverter
- NAND gate
- NOR gate
- AOI and OAI gate
- XOR gate
- Transmission gate
- Three-state buffer
- Latches and flip-flops

3. Software for hierarchical design of integrated circuits
General rules for using of CADENCE software package.

4. Design of IC with bottom-up method
Schematic of a circuit – from transistors to a circuit. Functional verification. Layout creation:
- Design rules, that is, compromise between yield of production and system performance
- Electrical parameters of layers
- Interconnections between IC and outside world
- Exemplary layouts
Layout verification and sending to fabrication.

Laboratory classes:

Laboratory

1. Design of an inverter – get acquainted with full CMOS IC design flow with bottom-up method in CADENCE environment
Schematic creation, choosing of elements parameters for obtain given assumptions (e.g. work frequency, energy consumption, area of design). Layout creation, verification of design and electrical rules meeting, layout validity by comparison with schematic (LVS). Extraction of basic and parasitic elements and simulation of the circuit in conditions close to reality.

2. Design of basic logic gates
Selection of gates parameters to satisfy given requirements (e.g. time and/or energy parameters, area of circuit).

3. Design of integrated functional blocks
Design of circuits with given functional properties with hierarchical method using.

Student workload (ECTS credits balance)
Student activity form Student workload
Summary student workload 100 h
Module ECTS credits 4 ECTS
Participation in lectures 20 h
Participation in laboratory classes 24 h
Preparation for classes 20 h
Realization of independently performed tasks 26 h
Preparation of a report, presentation, written work, etc. 10 h
Additional information
Method of calculating the final grade:

1. Warunkiem uzyskania pozytywnej oceny końcowej jest uzyskanie pozytywnej oceny z laboratorium oraz zaliczenie wykładu.
2. Obliczamy średnią ważoną z ocen z laboratorium (40%) i egzaminu (60%).
3. Wyznaczmy ocenę końcową na podstawie zależności:
if sr>4.75 then OK:=5.0 else
if sr>4.25 then OK:=4.5 else
if sr>3.75 then OK:=4.0 else
if sr>3.25 then OK:=3.5 else OK:=3
4. Jeżeli pozytywną ocenę z laboratorium uzyskano w pierwszym terminie i dodatkowo student był aktywny na wykładach, to ocena końcowa jest podnoszona o 0.5.

Prerequisites and additional requirements:

- Fundamentals of Physics,
- Electronic devices,
- Basic electronic circuits creation

Recommended literature and teaching resources:

1. A. Gołda, A. Kos, Projektowanie układów scalonych CMOS, WKŁ, Warszawa, 2010,
2. N.H.E. Weste, D.M. Harris, Integrated Circuit Design, Pearson, Boston, 2011.

Scientific publications of module course instructors related to the topic of the module:

1 Mikuła S. De Mey G., Kos A., Asynchronous control of modules activity in integrated systems for reducing peak temperature, Elsevier, Integration the VLSI journal 41, 2008, pp. 447-458

2 Mikuła. S., Kos A., Thermal Dynamics of Multicore Integrated Systems, IEEE Trans. On Components and Packaging Technologies, Vol. 33, No. 3, September 2010, pp. 524-534

3 Brzozowski I., Kos A., Low-power logic design based on gate driving way considering interconnections capacitances, Electrical Review, 2010, 86, nr 11a, pp. 102-106

4 Mikuła. S., Kos A., Analysis of integrated circuits thermal dynamics with point heating time, ELSEVIER, Microelectronics Journal, vol. 42, iss. 1, 2011, pp. 1-11

5 Jabłoński M, De Mey G., Kos A., Quad confoguration for improved thermal design of cascode current mirror, Electronics Letters, 19th January 2012, Vol. 48, No. 2, pp. 80-82

6 Boroń K., Kos A., Thermal model of selected parts of human hand and thermal touch screen for the blind, Metrology and Measurement Systems, Vol. XIX (2012), No. 3, pp. 593-602.

7 Gelmuda W. Kos A., Designing low-power embedded systems, Electronics World, Vol. 118, Issue 1915, July 2012, pp.18-20

8 Frankiewicz M., Kos A., Overheat protection circuit for high frequency processors, Bulletin of the Polish Academy of Science Technical Sciences, Vol. 60, No. 1, 2012, pp.55-59

9 De Mey G., Bogusławski B., Kos A., Unstable Inverse Heat Transfer Problems in Microelectronics, Acta Physica Polonica A, Vol. 123 (2013), No.4, pp.637-641

Additional information:

None